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1) Course Description
From the course catalog:
Introduces digital systems with lectures and labs on logic, flip flops, FPGAs, counters, timing, synchronization, and finite-state machines. Includes overview of accelerometers, gyros, time of flight and other modern sensors. Prepares students for the design and implementation of a final project of their choice: games, music, digital filters, wireless communications, video, or graphics. Extensive use of Verilog for describing and implementing digital logic designs. In person not required.
6.002 or 6.08 or 16.004 or permission of instructor. Basically we want some engineering maturity.
In general, the calendars will be kept up to date with schedules and due dates. As of right now, pretty much everythign for the semester is on the calendar. If anything looks sus, reach out and feel free to clarify...mistakes are possible.
Lectures are every Tuesday and Thursday at 2:30PM EDT and will be up to 90 minutes in length. Lecture room is 32-141.
3.2) Problem Sets (Psets)
There will generally be small problem sets that will be released at the end of one lecture and due before the next lectures. Yes, this means that you will sometimes get an assignment on Tuesday and it is due two days later on Thursday. They are not meant to be crazy long, but they exist to force some paced reflection on past material and prep for future material. Psets will be released on the site, but you are to upload your solutions/work through gradescope. They are manually graded and will be returned to you at a later date. They have a hard deadline (2:29pm, right before lecture on whatever day they are due) and late submissions will not be accepted.
Problem sets collectively are worth 16% of your final grade.
There are five lab assignments spread throughout the first portion of the class. See the calendar for particular dates of when they are released and when they are due. You work on these assignments in your own time (there is no "lab" sesssion), though feel free to come to office hours, etc. You need to do checkoffs with a staff member to get credit for the lab. This will usually involve demonstrating your simulations, device, and answering questions. Labs are done on your own as are checkoffs. Labs collectively make up 34% of your grade. The breakdown is as follows:
- Lab 1: 3% of final grade
- Lab 2: 5% of final grade
- Lab 3: 8% of final grade
- Lab 4: 10% of final grade
- Lab 5: 8% of final grade
You must have a non-zero score for all labs and all labs must be checked off in order to pass the class. A missing lab will result in a failing grade.
For 2021, labs can be done remotely since you have a kit, however checkoffs must be done in person.
4) Office Hours Calendar
Below is a calendar of office hours availability from staff. This will update and change from week to week depending on deadlines.
Office hours will be hybrid, so you can remote video in, however, staff will prioritize in-person students (in the lab) when the queue gets long.
There are Verilog textbooks out there, but honestly they're all getting outdated. Internet searches and StackOverflow are good starting points for most questions/references. In terms of particular Verilog things:
There will be no exams in 6.111. You are welcome.
7) Overall Grade
Your overall grade is based on the following breakdown:
- Psets: 16%
- Labs: 34%
- Participation: 2%
- Final Project (the project and keeping on track in it): 35%
- Proposal Presentation and Final Report: 13%
A large number of students do "A" level work and are, indeed, rewarded with a grade of "A". The corollary to this is that, since average performance levels are so high, punting any part of the subject can lead to a disappointing grade.
8) Late Submissions
- Psets are due when they are due. You can’t turn those in late (so don’t skip them!)
- Labs are due at the due date. However they can be turned in late with an increasing point penalty based on lateness. Every day late, they lose 20%. A few additional details on this:
- Lateness is calculated to the day (minutes and seconds do not come into play). So if lab is due on Thursday at 11:59pm and you do not finish it then, if you turn it in at any point on Friday, it is worth 80%
- Lateness is applied to each part of the lab individually. For hypothetical Lab N, if you get Checkoffs 1 and 2 done on time, and get Checkoff 3 done one day late, the lateness is only applied to Checkoff 3.
- Saturday and Sunday do not count in calculation of lateness since there are never office hours on that day.
If you have any extenuating circumstances that warrant an extension please go to S^3 and then reach out to Joe.