If you are a current student, please Log In for full access to the web site.
Note that this link will take you to an external site (https://shimmer.mit.edu) to authenticate, and then you will be redirected back to this page.
1) Course Description
From the course catalog:
Introduces digital systems with lectures and labs on logic, flip flops, FPGAs, counters, timing, synchronization, and finite-state machines. Includes overview of accelerometers, gyros, time of flight and other modern sensors. Prepares students for the design and implementation of a final project of their choice: games, music, digital filters, wireless communications, video, or graphics. Extensive use of Verilog for describing and implementing digital logic designs. In person not required.
6.002 or 6.08 or 16.004 or permission of instructor. Basically we want some engineering maturity.
Lectures are every Tuesday and Thursday at 2:30PM EDT and will be up to 90 minutes in lenght. They will take place on Zoom and will be recorded for later consumption if people need that.
3.2) Lecture PSets (LPsets)
There will generally be small Lecture PSets (Lpsets or LPsets or lpsets) that will be due between lectures. Yes, this means that you will sometimes get an assignment on Tuesday and it is due two days later on Thursday. They are not meant to be crazy long, but they exist. Pay attention to the calendar. Some run from Tuesday to Thursday, some from Thursday to Tuesday, and some an entire week (Tuesday to Tuesday or Thursday to Thursday) depending on the week and other assignments. Lpsets will be uploaded through gradescope, manually graded, and returned to you at a later date.
Lpsets collectively are worth 16% of your final grade, with each one worth an equal amount.
There are five lab assignments spread throughout the first portion of the class. See the calendar for particular dates of when they are released and when they are due. You work on these assignments in your own time (there is no "lab" sesssion), though feel free to come to office hours, etc. You need to do checkoffs with a staff member to get credit for the lab. This will usually involve demonstrating your simulations, device, and answering questions. Labs are done on your own as are checkoffs. Labs collectively make up 34% of your grade. The breakdown is as follows:
- Lab 1: 2% of final grade
- Lab 2: 5% of final grade
- Lab 3: 8% of final grade
- Lab 4: 11% of final grade
- Lab 5: 8% of final grade
You must have a non-zero score for all labs and all labs must be checked off in order to pass the class. A missing lab will result in a failing grade.
3.4) Final Project
4) Office Hours Calendar
Below is a calendar of office hours availability from staff. This will update and change from week to week depending on deadlines.
There are Verilog textbooks out there, but honestly they're all getting outdated. Internet searches and StackOverflow are good starting points for most questions/references. In terms of particular Verilog things:
There will be no exams in 6.111. You are welcome.
7) Overall Grade
Your overall grade is based on the following breakdown:
- Lpsets: 16%
- Labs: 34%
- Participation: 2%
- Final Project (the project and keeping on track in it): 35%
- Proposal Presentation and Final Report: 13%
A large number of students do "A" level work and are, indeed, rewarded with a grade of "A". The corollary to this is that, since average performance levels are so high, punting any part of the subject can lead to a disappointing grade.
8) Late submissions
- Lpsets are due when they are due. You can’t turn those in late (so don’t skip them!)
- Labs are due at a nominal time. Every day late, they lose 20%.
- BUT. You have five slack days that can be applied (you can use up to two on any lab). They will be applied after all labs are done to maximize benefit. Slack days can only be used on labs. Can’t use on final project stuff or Lpsets